An Efficient Implementation of Is-95 Cdma Reverse Link Transceiver: A Codesign Approach

An Efficient Implementation of IS-95 CDMA Reverse Link

Transceiver: A Codesign approach

Vinod Raman

Pankaj Bhagawat Department of Electrical Engineering Texas A&M University

Rabi Mahapatra Department of Computer Science Texas A&M University

ABSTRACT

We present a novel implementation scheme for IS-95 CDMA Reverse Link Transceiver based on Codesign principle. At functional level, the tasks are partitioned between a low-cost general-purpose processor and application specific DSP to optimize power-delay requirements. Our result show that a balanced Codesign strategy can help effective system implementation that can meet user’s specifications and provide flexibility for performance trade-off.

1.  INTRODUCTION

Code division multiple access (CDMA) is a modulation and multiple-access scheme based on spread-spectrum communication [1]. In this scheme, multiple users share the same frequency band at the same time, by spreading the spectrum of their transmitted signals, so that each user's signal is pseudo-orthogonal to the signals of the other users. In a CDMA system, each signal consists of a different pseudorandom binary sequence (called the spreading code) that modulates a carrier, spreading the spectrum of the waveform. A large number of CDMA signals share the same frequency spectrum. If CDMA is viewed in either the frequency or time domain, the multiple access signals overlap with each other.  However,  the  use  of  statistically  orthogonal  spreading codes separates the various signals in the code space.

CDMA technology is widely used in cell phones today. Therefore, the need for efficient, low power, embedded implementations of CDMA transceivers is quite pressing. Performance efficiency requires that the system be partitioned optimally between different kinds of processors. Power consumption is a critical issue in embedded systems; especially so in mobile phones since they operate at very low power levels. This necessitates the need for a low power implementation. Hence there is a need to strike a balance between ease of implementation, performance and power consumption.

System partitioning is an integral step in embedded system co- design methodology. Assignment of an operation to general purpose processor or application specific processor determines the delay and power consumption by the system. Efficient design of an embedded system entails optimization of this division of labor between a general purpose and application specific processor like a DSP. In this paper, we describe partitioning for an IS-95 CDMA Reverse Link Transceiver using XTENSA General-purpose processor [6] and TMS320C6X Digital Signal Processor [7].

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